Welcome to CORE-V Wally Discussions #253
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looking over wally-tool-chain-install.sh and it is decidely Ubuntu in flavor. Is there a RHEL 8 modified version making use of dnf, *-devel, and RHEL 8 named versions of the libraries and tools needed? I realize some of these tools may need to be compiled from source on RHEL 8 if there's not an equivalent. Not looking to avoid the effort, just don't want to re-invent what may already be available. |
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Hi,
Thanks for the Email. Our version currently uses buildroot but I am sure it can be easily ported to other flavors. We had a desire to port a RTOS but have not done this one yet. All items should be contained in the repository and if you need any help, let us know. Take care.
All my best,
James
… On Aug 11, 2023, at 11:12 AM, burkettttt ***@***.***> wrote:
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looking over wally-tool-chain-install.sh and it is decidely Ubuntu in flavor. Is there a RHEL 8 modified version making use of dnf, *-devel, and RHEL 8 named versions of the libraries and tools needed? I realize some of these tools may need to be compiled from source on RHEL 8 if there's not an equivalent. Not looking to avoid the effort, just don't want to re-invent what may already be available.
Thanks for your time.
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I think James answered with respect to booting buildroot Linux on the processor.
If the question is with respect to the development environment, we’ve had great difficulty getting Sail running reliably on RHEL and Sail is a required component of the riscof verification flow. The difficulties occurred even trying to build from source. Therefore we migrated to Ubuntu. If you are a RHEL and Sail whiz and can get them running reliably together, we’d be thrilled to add it.
David
… On Aug 11, 2023, at 9:57 AM, James E. Stine ***@***.***> wrote:
Hi,
Thanks for the Email. Our version currently uses buildroot but I am sure it can be easily ported to other flavors. We had a desire to port a RTOS but have not done this one yet. All items should be contained in the repository and if you need any help, let us know. Take care.
All my best,
James
> On Aug 11, 2023, at 11:12 AM, burkettttt ***@***.***> wrote:
>
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe
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> looking over wally-tool-chain-install.sh and it is decidely Ubuntu in flavor. Is there a RHEL 8 modified version making use of dnf, *-devel, and RHEL 8 named versions of the libraries and tools needed? I realize some of these tools may need to be compiled from source on RHEL 8 if there's not an equivalent. Not looking to avoid the effort, just don't want to re-invent what may already be available.
> Thanks for your time.
>
> —
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Thanks to both of you for the replies. David is closer to what I was looking for. I know RHEL, but Sail is something brand new to me. Systems Administrator in classroom support, not a wiz outside of that. Had a request to see about loading CVW on the RHEL systems. There are some restricted lab systems running UBUNTU, but not once I admin. I'll pass along your reply David and see what the Faculty and TAs want to do going forward. |
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Getting everything running for CORE-V Wally is not trivial and seems to break in different ways on each system we’ve tried to use it on. I would be happy to support installing on Ubuntu, especially so I can improve the installation documentation with any difficulties specific to your systems.
Take a look at the Sail installation and consider attempting to install it on your RHEL system. It has given us and others a lot of grief on that platform. I’ve spoken with the developer, and there is no immediate plan for better support.
David Harris
… On Aug 16, 2023, at 1:42 PM, burkettttt ***@***.***> wrote:
Thanks to both of you for the replies. David is closer to what I was looking for. I know RHEL, but Sail is something brand new to me. Systems Administrator in classroom support, not a wiz outside of that. Had a request to see about loading CVW on the RHEL systems. There are some restricted lab systems running UBUNTU, but not once I admin. I'll pass along your reply David and see what the Faculty and TAs want to do going forward.
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David: Appreciate the offer of help. I will certainly take you up on it. I need to step back from this project for a few weeks though because classes start on Monday and will be a bit chaotic. I'll get back to you when I start back on this. |
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Hi, I am a final year Computer Engineering student with a keen interest in computer architecture. I came across a project titled 'CORE-V Wally Technology Readiness Level 5' in the LFX mentorship program and would like to contribute to it. My skills include C, Python, and SystemVerilog. Could you provide more details about this project, along with study materials, references, or any guides to help me get started? Jian De |
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Jian,
Nice to meet you. The project description has everything I know about the project right now. The Wally Git repository and RISC-V specifications might give you more of a sense of the project.
David Harris
… On Jan 9, 2024, at 9:33 AM, Jian De ***@***.***> wrote:
Hi,
I am a final year Computer Engineering student with a keen interest in computer architecture. I came across a project titled 'CORE-V Wally Technology Readiness Level 5 <https://mentorship.lfx.linuxfoundation.org/project/cc564a0f-72d5-4588-ad83-0e5bb0257df2>' in the LFX mentorship program and would like to contribute to it. My skills include C, Python, and SystemVerilog. Could you provide more details about this project, along with study materials, references, or any guides to help me get started?
Jian De
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In the cache source code, there is a character mentioned as D$, I$ what is the meaning of this? |
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D$ and I$ refer to data cache and instruction cache respectively. Here's a bit of extra reading on the topic, if you're interested: https://en.m.wikipedia.org/wiki/Modified_Harvard_architecture |
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Thank you for your response. |
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Is there any specification or reference, I am trying to analyse the whole code, can anyone suggest. |
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In the code, they have mentioned RISC-V System on Chip Design Chapter 7 like that. Can I get the documentation of that book or can I know where to find it? |
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Thank you for your response, I have just started to understand the basics. So, I have to build the toolchain. |
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In lsu.sv file the output port LSUHWSTRB is connected with the output ports of ahbcacheinterface and ahbinterface instantiations. Can anyone explain how it works. |
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LSUHWSTRB is the HWSTRB signal from the LSU to the AHB port to control which bytes are written (for example, when doing a store halfword over a 64-bit interface). Wally is configurable to have a data cache or not (P.DCACHE_SUPPORTED). The logic to control HWSTRB is different in systems with and without a cache. Wally instantiates either ahbcacheinterface or ahbinterface, accordingly. |
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Thank you for your response. |
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DCACHE_SUPPORTED is set in the config file.
There’s a lot going on here that will be documented in the textbook.
What is your application for Wally?
If you’re an individual looking to experiment with open hardware, it would be easiest to wait until the book comes out next year.
If you are part of an organization looking for a collaboration, let’s talk about how to support you before the book is available.
Feel free to email me directly at my Harvey Mudd College address.
David Harris
… On Apr 3, 2024, at 9:37 PM, Zoro210 ***@***.***> wrote:
Thank you for your response.
So, how will the core know if there is cache or not and how the HWSTRB will be selected based on with or without cache?
I didn't find any logic regarding this.
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Thank you for your reply, I am an individual just trying to understand this
wally.
…On Thu, 4 Apr, 2024, 10:13 David Harris, ***@***.***> wrote:
DCACHE_SUPPORTED is set in the config file.
There’s a lot going on here that will be documented in the textbook.
What is your application for Wally?
If you’re an individual looking to experiment with open hardware, it would
be easiest to wait until the book comes out next year.
If you are part of an organization looking for a collaboration, let’s talk
about how to support you before the book is available.
Feel free to email me directly at my Harvey Mudd College address.
David Harris
> On Apr 3, 2024, at 9:37 PM, Zoro210 ***@***.***> wrote:
>
>
> Thank you for your response.
> So, how will the core know if there is cache or not and how the HWSTRB
will be selected based on with or without cache?
> I didn't find any logic regarding this.
>
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That is a great question. spitest hangs for me too.
We haven’t worked on demos like this, and I don’t think we have one. Everything in examples runs on Spike and uses printf, which doesn’t have hardware support in Wally. I will try to prepare an example of a C program that uses crt0.s with an exception handler, and uses the UART to print something. Are there any other features you are looking for in a demo?
… On Nov 26, 2024, at 12:53 AM, AishwaryaPrabhu1 ***@***.***> wrote:
hello, we are now using "wsim rv64gc custom" command to run the spitest in the custom directory present in the repository. When we are running this particular test in command mode, it is going to an infinite loop. So we tried running it in gui mode even then it is going to an infinite loop. Is there any other C testcase we can analyse to write our own C testcase.
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Thank you for your reply. It will be really useful if you can develop a C program for gpio for the same scenario. |
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@AishwaryaPrabhu1 I've made a PR with examples/C/hello and gpio. I modified the Berkeley syscalls.c slightly to print via the UART rather than with a system call, and found it still works in Spike as well. I haven't tested the gpio on hardware. Our wsim verilator flow seems to have just broken, so the PR is a draft right now. You can look at it anyway, and we will merge it when we figure out what happened to Verilator simulating individual ELF files. |
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@jordancarlin fixed wsim, which had never been working on a single ELF. PR should be ready now. |
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@AishwaryaPrabhu1 the PR has been merged and the new examples should both be in the examples directory. |
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Thank you so much! I got a really good understanding on the working flow of C testcase. |
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The rv64gc configuration of Wally doesn’t have many peripherals, and it’s easiest to test them if they aren’t multiplexed onto shared pins. You could add more peripherals and use iof to share them.
… On Dec 4, 2024, at 2:43 AM, AishwaryaPrabhu1 ***@***.***> wrote:
Thank you so much! I got a really good understanding on the working flow of C testcase.
I was going through gpio_apb.sv file, in which i noticed the pins iof0 & iof1 are not connected any peripherals. Is there any specific reason for these pins to be not connected, because as per my understanding we usually configure gpio pins with other peripherals.
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Hello, I want to write c testcase for spi, can I use the library files in cvw/fpga/zsbl , Or is there any other library file present. Since the old spitest case is not working, which was developed using these libraries. |
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Hello! |
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I haven’t looked at the zsbl library, but it might work.
The SPI code should look very much like the GPIO code. The base address of each peripheral is defined in config/rv64gc. The SPI is SiFive FE310 compatible, so google the FE310 datasheet and use the register map.
David Harris
… On Dec 6, 2024, at 11:44 PM, AishwaryaPrabhu1 ***@***.***> wrote:
Hello, I want to write c testcase for spi, can I use the library files in cvw/fpga/zsbl , Or is there any other library file present. Since the old spitest case is not working, which was developed using these libraries.
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Thank you for your reply, I have written a test case for spi and it is working. |
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There is a SiFive-compatible PLIC. The addresses are in the config directory, along with the IDs for the various peripherals. You do the usual configuration to route the desired peripheral interrupts through the PLIC to the external interrupt.
Everything else is generic RISC-V. You will need to look at crt0.S regarding enabling interrupts and what happens on the trap vector. None of this has been used yet, so you’ll probably need modifications.
There is a WALLY-init-lib.h file that shows an example of a simple interrupt handler.
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SPI_LOOPBACK_TEST defaults to 1 so that Wally can test its own SPI. Change it to 0, or make a new configuration with it being 0.
… On Dec 14, 2024, at 4:07 AM, AishwaryaPrabhu1 ***@***.***> wrote:
Hello!
I am writing a SPI C testcase in which I am driving values through my testbench to the SPIIn port in SPI & trying to collect it through SPIOut. I am not able to do this because the parameter "SPI_LOOPBACK_TEST" is configured high. But at the same time if I am writing directly into the transmit register through spi_txrx function in the library file (as I mentioned in my earlier comment) this process is working. Is there any specific reason for configuring "SPI_LOOPBACK_TEST" as high.
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Hello, in config file of rv64gc, "IROM_SUPPORTED = 0". I want to enable this and write a C testcase using ROM. What all process do I need to follow if I am enabling it. Kindly guide me. |
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Not sure you need this because the ram gets preloaded with your ELF in the
fpga or test bench.
If you do want this, I’d suggest using the boot rom. It defaults to address
1000. The reset vector should point to the start of the boot rom.
The main rom has primarily been tested in tiny configurations like rv32i
with no cache. You can try it by setting IROM.SUPPORTED=1. If you have RAM
populated at the same address, I don’t remember what loads to that address
will do.
…On Wed, Dec 18, 2024 at 3:15 AM AishwaryaPrabhu1 ***@***.***> wrote:
Hello, in config file of rv64gc, "IROM_SUPPORTED = 0". I want to enable
this and write a C testcase using ROM. What all process do I need to follow
if I am enabling it. Kindly guide me.
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Hi @davidharrishmc , I'm exploring Core Wally to get some inspiration. :) I noticed that the regfile uses the negedge clock. I remember, two years ago, when I implemented my own 5-stage pipeline CPU, I changed the regfile to use a posedge clock and extended the hazard logic to enable forwarding registers from the decode stage. Now, my question is: I don't have much experience with ASICs—why is it acceptable or advantageous to use a negedge clock for the regfile in this case? Here is my adjusted hazard logic... I learned everything from edX and your two videos: |
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Hi @stineje , I’ve been analyzing your project since yesterday. I’m not deeply involved yet, but I’m looking for patterns I can use pattern in my new project. I noticed an issue with the regfile that I addressed in my 5-stage pipelined design using the Harris approach—it didn’t require an extra cycle. Or am I missing something here? Thank you! Also, a quick mention of KianV! best regards, H.D. |
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I derived this from my edX slides. I also added forwarding checks in the decode stage, which allowed me to use posedge in the register file. @davidharrishmc |
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The negedge write allows read and write in the same cycle, avoiding the
cost of forwarding muxes. It is an old school design style. Usually systems
use posedge can everywhere now to simplify timing. The cost of the
forwarding muxes is small compared to all the other things in a
full-featured processor. However, the decode reg file path is not critical
so this is an easy optimization to make.
…On Sat, Jan 4, 2025 at 3:03 PM splinedrive ***@***.***> wrote:
Hi @davidharrishmc <https://github.com/davidharrishmc> ,
I'm exploring Core Wally to get some inspiration. :) I noticed that the
regfile uses the negedge clock. I remember, two years ago, when I
implemented my own 5-stage pipeline CPU, I changed the regfile to use a
posedge clock and extended the hazard logic to forward registers from the
decode stage.
Now, my question is: I don't have much experience with ASICs—why is it
acceptable or advantageous to use a negedge clock for the regfile in this
case?
Here is my adjusted hazard logic... I learned everything from edX and your
two videos:
https://github.com/splinedrive/kianRiscV/blob/master/archive/harris_baremetal_stuff/kianv_harris_pipelined_edition/processor/hazard_unit.sv
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I had a feeling it was something like this, but I never really looked into the timings... edX didn't cover this in much detail. Thank you |
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@davidharrishmc |
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I see! |
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If I place the muxes for enabling forwarding in the decode stage, and the design operates with a single-phase clock, would it be possible to run the design at 40 MHz on the Arty A7 instead of 20 MHz? |
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That won't double the clock speed unfortunately. There are several critical paths, all of which can be improved to increase clock speed. I don't recall the exact order of these and they may have changed but they are...
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Thank you for the clarification. I will work on my new CPU with a single-phase clock only, just like I did two years ago after edX. I am adopting the hierarchy abstraction and file structure from your project—it’s really impressive how you’ve organized it. |
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