From 25511f7110ec3bd93d16ede937cd9ba27067b52e Mon Sep 17 00:00:00 2001
From: rmsyn <github@weathered-steel.dev>
Date: Wed, 18 Dec 2024 03:44:37 +0000
Subject: [PATCH 1/2] riscv: define mstatush CSR with macro helpers

Uses CSR macro helpers to define the `mstatush` CSR register.
---
 riscv/src/register/mstatush.rs | 28 +++++++++++++---------------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/riscv/src/register/mstatush.rs b/riscv/src/register/mstatush.rs
index 5fbab3b8..b90878a6 100644
--- a/riscv/src/register/mstatush.rs
+++ b/riscv/src/register/mstatush.rs
@@ -2,28 +2,26 @@
 
 pub use super::mstatus::Endianness;
 
-/// mstatus register
-#[derive(Clone, Copy, Debug)]
-pub struct Mstatush {
-    bits: usize,
+read_write_csr! {
+    /// mstatus register
+    Mstatush: 0x310,
+    mask: 0x30,
 }
 
-impl Mstatush {
+read_write_csr_field! {
+    Mstatush,
     /// S-mode non-instruction-fetch memory endianness
-    #[inline]
-    pub fn sbe(&self) -> Endianness {
-        Endianness::from(self.bits & (1 << 4) != 0)
-    }
+    sbe,
+    Endianness: [4:4],
+}
 
+read_write_csr_field! {
+    Mstatush,
     /// M-mode non-instruction-fetch memory endianness
-    #[inline]
-    pub fn mbe(&self) -> Endianness {
-        Endianness::from(self.bits & (1 << 5) != 0)
-    }
+    mbe,
+    Endianness: [5:5],
 }
 
-read_csr_as_rv32!(Mstatush, 0x310);
-write_csr_rv32!(0x310);
 set_rv32!(0x310);
 clear_rv32!(0x310);
 

From ed2a9eaa38e1af56439b4e961012014322e63fb0 Mon Sep 17 00:00:00 2001
From: rmsyn <github@weathered-steel.dev>
Date: Wed, 18 Dec 2024 04:04:12 +0000
Subject: [PATCH 2/2] riscv: add basic unit tests for mstatush

Adds a basic unit-tests for the `mstatush` CSR.
---
 riscv/CHANGELOG.md             |  1 +
 riscv/src/register/mstatush.rs | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index e146a0c5..85de39ee 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -25,6 +25,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use CSR helper macros to define `misa` register
 - Use CSR helper macros to define `mip` register
 - Use CSR helper macros to define `mstatus` register
+- Use CSR helper macros to define `mstatush` register
 
 ## [v0.12.1] - 2024-10-20
 
diff --git a/riscv/src/register/mstatush.rs b/riscv/src/register/mstatush.rs
index b90878a6..cc64598e 100644
--- a/riscv/src/register/mstatush.rs
+++ b/riscv/src/register/mstatush.rs
@@ -42,3 +42,20 @@ pub unsafe fn set_mbe(endianness: Endianness) {
         Endianness::LittleEndian => _clear(1 << 5),
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mstatush() {
+        let mut m = Mstatush::from_bits(0);
+
+        [Endianness::LittleEndian, Endianness::BigEndian]
+            .into_iter()
+            .for_each(|endianness| {
+                test_csr_field!(m, sbe: endianness);
+                test_csr_field!(m, mbe: endianness);
+            });
+    }
+}