GitHub - Andrew-Hany/FemtoRV32-Piplined-Processor: The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.

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The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.

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The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.

verilog vivado testbench pipeline-cpu risc-processor riscv32

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