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  1. OpenROAD-for-Low-cost-ASIC-design-and-Rapid-Innovation OpenROAD-for-Low-cost-ASIC-design-and-Rapid-Innovation Public

    This workshop was organised by IIT Guwahati collabarted with MeitY, NINE Labs, Electronics India.

    Verilog 3

  2. Design-and-Analysis-of-a-CMOS-Inverter-Using-the-Sky130PDK Design-and-Analysis-of-a-CMOS-Inverter-Using-the-Sky130PDK Public

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  3. RTL-to-GDSII-ASIC-design-of-Counter RTL-to-GDSII-ASIC-design-of-Counter Public

    The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK).. The tools used in this p…

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  4. Physical-Design Physical-Design Public

  5. msvsd4bitservoadc msvsd4bitservoadc Public

  6. Signing-off-Timing-Analysis Signing-off-Timing-Analysis Public