- 👋 Hi, I’m @Pavan-Kendaganna-Swamy
- 👀 I’m Master's Degree Graduate in Electrical Engineering with a specialization in VLSI from ASU. I’m looking to collaborate on RTL coding and coding skills required for VLSI Engineer
- 📫 You can reach me at pkendaga@asu.edu
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3StagePipeline
3StagePipeline PublicThis Repo is to demonstrate RTL to GDSII design implementation
Verilog
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