a high performance library for building cache simulators
Trace-driven cache memory simulator with LRU, MRU, RR and Belady replacement policies.
This is a simulator for access strategies for distributed caching. The simulator considers a user who is equipped by several caches, and receives from them periodical updates about the cached content. The problem and algorithms implemented here are detailed in the paper: I. Cohen, G. Einziger, R. Friedman, and G. Scalosub, “Access Strategies for…
A C++11 Based CDN cache simulator
This C project is a cache simulation of a CPU containing L1D, L1I and L2 caches. It takes an image of memory and a memory trace as input, simulates the hit/miss behavior of a cache memory on this trace, and outputs the total number of hits, misses and evictions for each cache type along with the content of each cache at the end.
CPU Cache Simulation using gem5
Cache simulation in order to obtain performance metrics
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