In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.

MIPS Multicycle CPU design in Verilog

Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.

Processor supporting ARM architecture made in VHDL as a part of COL216 - Computer Architecture

Implemented additional operations for a Multicycle ARM Processor, as presented in Digital Design and Computer Architecture by Harris & Harris

Minimalist 8 bit multicycle RISC CPU

ARM Multicycle Processor - 32 bit Assembly instructions - VHDL - Arithmetic and Logical operations, Memory read and write - Vivado

🎓💻University of Tehran Computer Architecture Course Projects - Spring 2021

Multicycle and pipeline implementations for a RISC architecture in VHDL - EE309 Autumn 2017, IIT Bombay

MultiCycle and Pipelined Processor designed for the course Computer Organisation of TUC

Simple Multicycle Processor Similar to MIPS in Verilog

in this project we have implemented MIPS multicycle projects using Vivado

多周期CPU(MIPS指令集), 支持其中54条指令. (From 同济大学计算机组成原理课程设计)

Computer Architecture Lab projects with various fundamental concepts, including multi-cycle MIPS processors and PIC32 microcontroller programming.

VHDL implementation of multicycle and pipelined RISC architecture - EE309 Autumn 2018, IIT Bombay

Project of a Verilog implementation of a multicycle processor for the discipline of Computer Architeture and Design II

multi-cycle-processor based on Micro-Program with systemverilog

A project to design and simulate a 16-bit RISC Multicycle Processor

PUCRS T1 Organizacao e Arquitetura de Computadores 2 2017/2

Implementação de uma CPU multiciclo