Divide

.github/workflows/default.yml

@@ -1,9 +1,9 @@
 name: CI
 on:
   push:
-    branches: [ main ]
+    branches: [ main, divide ]
   pull_request:
-    branches: [ main ]
+    branches: [ main, divide ]
 
 
 jobs:
@@ -72,8 +72,8 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        unit: [lsu, alu, mul, sld, elem, csr, misc]
-        main_core: [ibex, cv32e40x]
+        unit: [lsu, alu, mul, sld, elem, csr, misc, div]
+        main_core: [ibex]
     steps:
       - uses: actions/checkout@v2
         with:

.github/workflows/main.yml

@@ -0,0 +1,125 @@
+name: CI
+on:
+  push:
+    branches: [ main ]
+  pull_request:
+    branches: [ main ]
+
+
+jobs:
+  verilator:
+    runs-on: ubuntu-22.04
+    steps:
+      - uses: actions/cache@v2
+        id: cache-verilator
+        with:
+          path: /opt/verilator
+          key: ubuntu-22_04-verilator-4_210
+
+      - name: Install Verilator
+        if: steps.cache-verilator.outputs.cache-hit != 'true'
+        run: |
+          sudo apt-get update
+          sudo apt-get install git perl python3 g++ flex bison ccache libfl2 libfl-dev zlib1g zlib1g-dev
+          git clone https://github.com/verilator/verilator
+          unset VERILATOR_ROOT
+          cd verilator
+          git checkout tags/v4.210
+          autoconf
+          ./configure --prefix /opt/verilator
+          make
+          sudo make install
+          df -h
+          cd ..
+          rm -rf verilator
+
+
+  lint:
+    needs: verilator
+    runs-on: ubuntu-22.04
+    steps:
+      - uses: actions/checkout@v2
+        with:
+          submodules: false
+
+      - uses: actions/cache@v2
+        id: cache-verilator
+        with:
+          path: /opt/verilator
+          key: ubuntu-22_04-verilator-4_210
+
+      - name: Abort if no cache
+        if: steps.cache-verilator.outputs.cache-hit != 'true'
+        run: exit 1
+
+      - name: Install packages
+        run: |
+          sudo apt-get update
+          sudo apt-get install git perl python3 g++ ccache libfl2 libfl-dev zlib1g zlib1g-dev
+
+      - name: Install verible and lint
+        run: |
+          curl -sSL https://api.github.com/repos/chipsalliance/verible/releases/latest | grep browser_download_url | grep Ubuntu-20.04 | cut -d '"' -f 4 | wget -qi -
+          mkdir verible
+          tar -xf verible*.tar.gz -C verible --strip-components=1
+          export PATH=$PATH:$PWD/verible/bin:/opt/verilator/bin
+          cd test && make lint
+
+
+  unit:
+    needs: verilator
+    runs-on: ubuntu-22.04
+    strategy:
+      fail-fast: false
+      matrix:
+        unit: [lsu, alu, mul, sld, elem, csr, misc]
+        main_core: [ibex, cv32e40x]
+    steps:
+      - uses: actions/checkout@v2
+        with:
+          submodules: true
+
+      - uses: actions/cache@v2
+        id: cache-verilator
+        with:
+          path: /opt/verilator
+          key: ubuntu-22_04-verilator-4_210
+
+      - name: Abort if no cache
+        if: steps.cache-verilator.outputs.cache-hit != 'true'
+        run: exit 1
+
+      - name: Install packages
+        run: |
+          sudo apt-get update
+          sudo apt-get install git perl python3 g++ ccache libfl2 libfl-dev zlib1g zlib1g-dev
+          sudo apt-get install srecord llvm-14 clang-14
+          sudo ln -sf /usr/bin/llvm-objdump-14 /usr/bin/llvm-objdump
+          sudo ln -sf /usr/bin/llvm-objcopy-14 /usr/bin/llvm-objcopy
+
+      - name: Run tests
+        shell: bash {0} # disable fail-fast behavior
+        run: |
+          export PATH=$PATH:/opt/verilator/bin:/opt/riscv-gcc/bin
+          verilator --version
+          retval=0
+          while IFS= read -ra line; do
+            if [ -z "$line" ] || [ "${line:0:1}" = "#" ]; then
+              continue
+            fi
+            echo "$line" > test/${{ matrix.unit }}/test_configs.conf
+            vcd=`echo "${{ matrix.unit }}_${{ matrix.main_core }}_${line}.vcd" | sed 's/  */_/g'`
+            make -C test ${{ matrix.unit }} CORE=${{ matrix.main_core }} FULL_LOG=1 TRACE_VCD=$vcd
+            if [ $? -ne 0 ]; then
+              retval=1
+            fi
+          done < .github/test_configs.conf
+          exit $retval
+
+      - name: Archive VCD trace files
+        if: failure()
+        uses: actions/upload-artifact@v3
+        with:
+          name: vcd-trace-files
+          path: |
+            test/${{ matrix.unit }}/*.vcd

.gitignore

@@ -26,4 +26,4 @@
 *.fst
 *.fst.hier
 *.gtkw
-vproc_config.sv
+

config.mk

@@ -15,7 +15,7 @@
 #  - VPROC_PIPELINES: Defines the vector pipelines. Each pipeline is defined by
 #    a string of the form "WIDTH:UNIT[,UNIT]*" where WIDTH is the width in bits
 #    of the pipeline's datapath and each occurence of UNIT selects one of the
-#    vector execution units (either VLSU, VALU, VMUL, VSLD, or VELEM).
+#    vector execution units (either VLSU, VALU, VMUL, VSLD, VELEM, or VDIV).
 #  - VPROC_CONFIG: Sets default values for the other parameters (that can be
 #    individually overriden) depending on the desired number of vector
 #    pipelines (choose 1, 2, 3, or 5 pipelines by setting this variable to
@@ -28,26 +28,26 @@ ifeq ($(VPROC_CONFIG), compact)
   VPORT_POLICY    ?= some
   VMEM_W          ?= 32
   VREG_W          ?= 128
-  VPROC_PIPELINES ?= $(VMEM_W):VLSU,VALU,VMUL,VSLD,VELEM
+  VPROC_PIPELINES ?= $(VMEM_W):VLSU,VALU,VMUL,VSLD,VELEM,VDIV
 else
 ifeq ($(VPROC_CONFIG), dual)
   VPORT_POLICY    ?= some
   VMEM_W          ?= 32
   VREG_W          ?= 128
-  VPROC_PIPELINES ?= $(VMEM_W):VLSU,VALU,VELEM $(VPIPE_W_VMUL):VMUL,VSLD
+  VPROC_PIPELINES ?= $(VMEM_W):VLSU,VALU,VELEM,VDIV $(VPIPE_W_VMUL):VMUL,VSLD
 else
 ifeq ($(VPROC_CONFIG), triple)
   VPORT_POLICY    ?= some
   VMEM_W          ?= 32
   VREG_W          ?= 256
-  VPROC_PIPELINES ?= $(VMEM_W):VLSU $(VPIPE_W_DFLT):VALU,VELEM $(VPIPE_W_VMUL):VMUL,VSLD
+  VPROC_PIPELINES ?= $(VMEM_W):VLSU $(VPIPE_W_DFLT):VALU,VELEM,VDIV $(VPIPE_W_VMUL):VMUL,VSLD
 else
 ifeq ($(VPROC_CONFIG), legacy)
   VPORT_POLICY    ?= some
   VMEM_W          ?= 32
   VREG_W          ?= 128
   VPROC_PIPELINES ?= $(VMEM_W):VLSU $(VPIPE_W_DFLT):VALU $(VPIPE_W_VMUL):VMUL                     \
-                                    $(VPIPE_W_DFLT):VSLD 32:VELEM
+                                    $(VPIPE_W_DFLT):VSLD 32:VELEM $(VPIPE_W_DFLT):VDIV
 else
 $(error Unknown vector coprocessor configuration $(VPROC_CONFIG))
 endif
@@ -102,7 +102,7 @@ $(VPROC_CONFIG_PKG):
 	    width=`echo $$pipe | cut -d ":" -f 1`;                                                    \
 	    unit_str=`echo $$pipe | cut -d ":" -f 2 | sed 's/,/, /g'`;                                \
 	    unit_mask=`echo $$pipe | cut -d ":" -f 2 | sed 's/,/ | /g' |                              \
-	               sed "s/V\(LSU\|ALU\|MUL\|SLD\|ELEM\)/(UNIT_CNT'(1) << UNIT_\1)/g"`;            \
+	               sed "s/V\(LSU\|ALU\|MUL\|SLD\|ELEM\|DIV\)/(UNIT_CNT'(1) << UNIT_\1)/g"`;       \
 	    vport_cnt=1;                                                                              \
 	    if echo "$$pipe" | grep -q "VMUL" && [ $$(($$width * 4)) -gt "$(VREG_W)" ]; then          \
 	        vport_cnt=2;                                                                          \
@@ -180,6 +180,7 @@ $(VPROC_CONFIG_PKG):
 	echo "    parameter int unsigned VLSU_QUEUE_SZ               = 4;"                      >>$@; \
 	echo "    parameter bit [VLSU_FLAGS_W-1:0] VLSU_FLAGS        = '0;"                     >>$@; \
 	echo "    parameter mul_type     MUL_TYPE                    = MUL_GENERIC;"            >>$@; \
+	echo "    parameter div_type     DIV_TYPE                    = DIV_GENERIC;"            >>$@; \
 	echo ""                                                                                 >>$@; \
 	echo "    parameter int unsigned INSTR_QUEUE_SZ              = 2;"                      >>$@; \
 	echo "    parameter bit [BUF_FLAGS_W-1:0] BUF_FLAGS          = $${buf_flags};"          >>$@; \

demo/rtl/demo_top.sv

@@ -4,7 +4,7 @@
 
 
 module demo_top #(
-        parameter              RAM_FPATH      = "",
+        parameter              RAM_FPATH      = "/home/hfaroo9/ece498hk-RISCV-V-Extension/src/vicuna/sim/files.txt",
         parameter int unsigned RAM_SIZE       = 262144,
         parameter bit          DIFF_CLK       = 1'b0,
         parameter real         SYSCLK_PER     = 0.0,
@@ -88,8 +88,8 @@ module demo_top #(
     vproc_top #(
         .MEM_W        ( 32                          ),
         .VMEM_W       ( 32                          ),
-        .VREG_TYPE    ( vproc_pkg::VREG_XLNX_RAM32M ),
-        .MUL_TYPE     ( vproc_pkg::MUL_XLNX_DSP48E1 )
+        .VREG_TYPE    ( vproc_pkg::VREG_GENERIC ),
+        .MUL_TYPE     ( vproc_pkg::MUL_GENERIC )
     ) vproc (
         .clk_i        ( clk                         ),
         .rst_ni       ( rst_n                       ),

prim/rtl/dv_fcov_macros.svh

@@ -0,0 +1,113 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Include FCOV RTL by default. Disable it for synthesis and where explicitly requested (by defining
+// DV_FCOV_DISABLE).
+`ifdef SYNTHESIS
+  `define DV_FCOV_DISABLE
+`elsif YOSYS
+  `define DV_FCOV_DISABLE
+`endif
+
+// Disable instantiations of FCOV coverpoints or covergroups.
+`ifdef VERILATOR
+  `define DV_FCOV_DISABLE_CP
+`elsif DV_FCOV_DISABLE
+  `define DV_FCOV_DISABLE_CP
+`endif
+
+// Instantiates a covergroup in an interface or module.
+//
+// This macro assumes that a covergroup of the same name as the NAME_ arg is defined in the
+// interface or module. It just adds some extra signals and logic to control the creation of the
+// covergroup instance with ~bit en_<cg_name>~. This defaults to 0. It is ORed with the external
+// COND_ signal. The testbench can modify it at t = 0 based on the test being run.
+// NOTE: This is not meant to be invoked inside a class.
+//
+// NAME_ : Name of the covergroup.
+// COND_ : External condition / expr that controls the creation of the covergroup.
+// ARGS_ : Arguments to covergroup instance, if any. Args MUST BE wrapped in (..).
+`ifndef DV_FCOV_INSTANTIATE_CG
+`ifdef DV_FCOV_DISABLE_CP
+  `define DV_FCOV_INSTANTIATE_CG(NAME_, COND_ = 1'b1, ARGS_ = ())
+`else
+  `define DV_FCOV_INSTANTIATE_CG(NAME_, COND_ = 1'b1, ARGS_ = ()) \
+    bit en_``NAME_ = 1'b0; \
+    NAME_ NAME_``_inst; \
+    initial begin \
+      /* The #1 delay below allows any part of the tb to control the conditions first at t = 0. */ \
+      #1; \
+      if ((en_``NAME_) || (COND_)) begin \
+        $display("%0t: (%0s:%0d) [%m] %0s", $time, `__FILE__, `__LINE__, \
+                 {"Creating covergroup ", `"NAME_`"}); \
+        NAME_``_inst = new``ARGS_; \
+      end \
+    end
+`endif
+`endif
+
+// Creates a coverpoint for an expression where only the expression true case is of interest for
+// coverage (e.g. where the expression indicates an event has occured).
+`ifndef DV_FCOV_EXPR_SEEN
+`ifdef DV_FCOV_DISABLE_CP
+  `define DV_FCOV_EXPR_SEEN(NAME_, EXPR_)
+`else
+  `define DV_FCOV_EXPR_SEEN(NAME_, EXPR_) cp_``NAME_: coverpoint EXPR_ { bins seen = {1}; }
+`endif
+`endif
+
+// Creates a SVA cover that can be used in a covergroup.
+//
+// This macro creates an unnamed SVA cover from the property (or an expression) `PROP_` and an event
+// with the name `EV_NAME_`. When the SVA cover is hit, the event is triggered. A coverpoint can
+// cover the `triggered` property of the event.
+`ifndef DV_FCOV_SVA
+`ifdef DV_FCOV_DISABLE
+  `define DV_FCOV_SVA(EV_NAME_, PROP_, CLK_ = clk_i, RST_ = rst_ni)
+`else
+  `define DV_FCOV_SVA(EV_NAME_, PROP_, CLK_ = clk_i, RST_ = rst_ni) \
+    event EV_NAME_; \
+    cover property (@(posedge CLK_) disable iff (RST_ == 0) (PROP_)) begin \
+      -> EV_NAME_; \
+    end
+`endif
+`endif
+
+// Coverage support is not always available but it's useful to include extra fcov signals for
+// linting purposes. They need to be marked as unused to avoid warnings.
+`ifndef DV_FCOV_MARK_UNUSED
+  `define DV_FCOV_MARK_UNUSED(TYPE_, NAME_) \
+    TYPE_ unused_fcov_``NAME_; \
+    assign unused_fcov_``NAME_ = fcov_``NAME_;
+`endif
+
+// Define a signal and expression in the design for capture in functional coverage
+`ifndef DV_FCOV_SIGNAL
+`ifdef DV_FCOV_DISABLE
+  `define DV_FCOV_SIGNAL(TYPE_, NAME_, EXPR_)
+`else
+  `define DV_FCOV_SIGNAL(TYPE_, NAME_, EXPR_) \
+    TYPE_ fcov_``NAME_; \
+    assign fcov_``NAME_ = EXPR_; \
+    `DV_FCOV_MARK_UNUSED(TYPE_, NAME_)
+`endif
+`endif
+
+// Define a signal and expression in the design for capture in functional coverage depending on
+// design configuration. The input GEN_COND_ must be a constant or parameter.
+`ifndef DV_FCOV_SIGNAL_GEN_IF
+`ifdef DV_FCOV_DISABLE
+  `define DV_FCOV_SIGNAL_GEN_IF(TYPE_, NAME_, EXPR_, GEN_COND_, DEFAULT_ = '0)
+`else
+  `define DV_FCOV_SIGNAL_GEN_IF(TYPE_, NAME_, EXPR_, GEN_COND_, DEFAULT_ = '0) \
+    TYPE_ fcov_``NAME_; \
+    if (GEN_COND_) begin : g_fcov_``NAME_ \
+      assign fcov_``NAME_ = EXPR_; \
+    end else begin : g_no_fcov_``NAME_ \
+      assign fcov_``NAME_ = DEFAULT_; \
+    end \
+    `DV_FCOV_MARK_UNUSED(TYPE_, NAME_)
+`endif
+`endif
+