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wt_axi_adapter: Fix addr width parametrisation #2697

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Jan 10, 2025
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wt_axi_adapter: Fix addr width parametrisation #2697

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6 changes: 3 additions & 3 deletions core/cache_subsystem/wt_axi_adapter.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -142,7 +142,7 @@ module wt_axi_adapter
axi_wr_data[0] = {(CVA6Cfg.AxiDataWidth/CVA6Cfg.XLEN){dcache_data.data}};
axi_wr_user[0] = dcache_data.user;
// Cast to AXI address width
axi_wr_addr = {{CVA6Cfg.AxiAddrWidth-CVA6Cfg.PLEN{1'b0}}, dcache_data.paddr};
axi_wr_addr = CVA6Cfg.AxiAddrWidth'(dcache_data.paddr);
axi_wr_size = dcache_data.size;
axi_wr_req = 1'b0;
axi_wr_blen = '0;// single word writes
Expand All @@ -167,15 +167,15 @@ module wt_axi_adapter
// arbiter mux
if (arb_idx) begin
// Cast to AXI address width
axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, dcache_data.paddr};
axi_rd_addr = CVA6Cfg.AxiAddrWidth'(dcache_data.paddr);
// If dcache_data.size MSB is set, we want to read as much as possible
axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size;
if (dcache_data.size[2]) begin
axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0];
end
end else begin
// Cast to AXI address width
axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, icache_data.paddr};
axi_rd_addr = CVA6Cfg.AxiAddrWidth'(icache_data.paddr);
axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill
if (!icache_data.nc) begin
axi_rd_blen = AxiRdBlenIcache[AxiBlenWidth-1:0];
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